Design of Low Noise SIPC LC - QVCO for IEEE 802 . 11 a Application in 0 . 18 μ m CMOS Technology

This paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized in both m g − pMOS cross coupled switching stage and m g − complementary stage. A stacked spiral inductor with a Q factor of 5.8 and a pMOS based diode connected varactor with 32% of tuning range utilized in realizing the resonator tank. The complementary and the single coupled pMOS based LC-QVCO exhibits a tuning range of 3.2-3.6GHz and 3-4GHz respectively. Implemented in 0.18μm technology the pMOS single coupled SIPC based LC-QVCO indicates a phase noise of -113.5dBc/Hz at 1MHz of offset frequency, an enhancement of 3dBc/Hz from its conventional counterpart, whereas the complementary SIPC LCQVCO architecture exhibits a phase noise of -114.3dBc/Hz, an enhancement of 1dBc/Hz from its conventional counterpart at 1MHz of offset frequency. The single coupled pMOS based SIPC QVCO and the complementary SIPC LC-QVCO architecture dissipates 14.6mW and 11.0mW of power respectively. Keywords—LC-QVCO, phase noise, RF CMOS, SIPC-QVCO.